Integrated circuit devices have been subject to ever increasing susceptibility to damage from applications of excessive voltages, for example, by electrostatic discharge (ESD) events. This susceptibility is due, in large part, to ever decreasing gate oxide thicknesses which have resulted as very large scale integration (VLSI) circuit geometries continued to shrink. In particular, during an ESD event, charge is transferred between one or more pins of the integrated circuit to another conducting object in a time period that is typically less than one microsecond. This charge transfer can generate voltages that are large enough to break down insulating film (e.g., gate oxides) on the device, or can dissipate sufficient energy to cause electrothermal failures in the device. Such failures include contact spiking, silicon melting, or metal interconnect melting.
There have been many attempts made in the prior art to protect semiconductor devices, with particular attention to the problem of protecting field effect transistor devices from such ESD events. In the early days of MOS technology, a simple clamp was utilized such that a high voltage or ESD event on a pad or input pin associated with the integrated circuit resulted in “clamping” the voltage to ground with use of simple clipping diodes. Further, structures were incorporated in the circuitry associated with one or more of the input/output (IO) circuits that utilized reverse breakdown semiconductor junctions that would become conductive at high voltages. However, these devices sometimes prove to be insufficient to completely absorb the energy due to the conductivity therethrough or the speed thereof.
Recent ESD devices utilize clamping transistors that are turned on in the event of an ESD event. The control circuitry for this transistor typically includes a resistor and capacitor connected in series between the power supply and ground. Whenever an ESD event occurred that either pulled the pad below ground or above the supply terminal, the pn junction associated with a drive transistor, for example, on the pad would be forward biased and cause the ESD transistor to turn on and clamp the output across the output drive transistors to prevent damage thereto. However, the circuitry must be added to each I/O circuit and corresponding pad.